The present invention relates to a structure for measuring mask and layer alignment in semiconductor fabrication processes.
A non-volatile memory cell is a memory cell that retains its stored information even if power is removed from the cell. In a conventional nonvolatile memory cell, a floating gate structure is commonly incorporated to provide this information storage function. FIG. 1 shows an example of a conventional floating gate memory cell 100. Memory cell 100 comprises a polysilicon floating gate 121 surrounded by an insulation material (e.g. silicon dioxide) 150. Floating gate 121 is located over a portion (channel) of a p-type body region 113 extending between an n-type source region 111 and an n-type drain region 112, all of which are formed in a substrate (e.g. silicon wafer) 101. A control gate 120 is located on the portion of insulation material 150 over floating gate 121. Source region 111, drain region 112, and control gate 120 are coupled to receive a source voltage Vs, a drain voltage Vd, and a gate voltage Vg, respectively.
Current between source region 111 and drain region 112 is controlled by the programmed/erased state of floating gate 121. This programmed/erased state is determined by the number of electrons stored (captured) in floating gate 121. In an unprogrammed state, a gate voltage Vg applied to control gate 120 controls the current flow between source region 111 and drain region 112 (i.e. memory cell 100 conducts when voltage Vg is HIGH, and does not conduct when voltage Vg is LOW). To program memory cell 100, electrons are injected into floating gate 121 until it stores a net negative charge that is sufficient to shift the threshold voltage of memory cell 100. Once programmed, memory cell 100 is nonconducting even when gate voltage Vg is HIGH.
Floating gate memory devices such as memory cell 100 typically require a relatively high voltage (i.e. substantially higher than the normal operating voltage of the IC) to inject electrons into (i.e. program) the floating gate. For example, a common operating supply voltage for modern integrated circuit (IC) devices is 3.3V. In such a case, unprogrammed memory cell 100 would be turned on (i.e. conduct current) with source region 111 at ground voltage and control gate 120 and drain region 112 both at 3.3V. However, to program memory cell 100, a programming voltage of 7.5V or greater might be required at control gate 120, with drain region 112 being held at 3.3V and source region 111 being held at ground voltage.
Because of this elevated programming voltage, conventional floating gate memory cells increase chip design complexity. Charge pump or other voltage enhancement circuits must be included into the IC design to provide the programming voltage, while isolation circuitry must be incorporated to prevent the raised voltages from damaging regular (non-memory) transistors in the IC. Floating gate memory cells also increase chip manufacturing complexity, as the floating gates are formed by an extra polysilicon deposition step that regular transistors do not require.
Accordingly, it is desirable to provide a nonvolatile memory cell that does not require an elevated programming voltage and does not require additional processing steps.
The present invention provides a nonvolatile memory cell that does not include a floating gate, and therefore can be fabricated using the same process steps as regular transistors in an IC. Also, the nonvolatile memory cell of the present invention can be programmed without the use of elevated programming voltages, thereby simplifying the IC design.
A nonvolatile memory cell in accordance with an embodiment of the present invention comprises a diffusion region formed in a silicon substrate, source and drain regions formed in the diffusion region, and a gate heating structure spanning the diffusion region between the source and drain regions. According to an aspect of the present invention, the gate heating structure comprises an oxide layer that overlies the diffusion region, a doped polysilicon layer that overlies the oxide layer, and a metal silicide layer that overlies the polysilicon layer. Two gate contacts are coupled to the gate heating structure, one at each end of the metal silicide layer outside the channel region. According to an aspect of the invention, the metal silicide layer is a TiSi2 layer. According to another aspect of the invention, the metal silicide layer is a CoSi2 layer.
In an unprogrammed state, the memory cell of the present invention functions as a normal MOS transistor. A control voltage is applied to both gate contacts to control current flow between the source and drain regions. To program the cell, different voltages are applied to the gate contacts to provide a programming voltage across the gate heating structure. The programming voltage is selected to create enough heating in the TiSi2 layer to cause localized dopant atom movement. The heating structure is configured such that the programming voltage is less than or equal to standard on-chip voltages. The resultant dopant atom distribution is sufficient to affect the transistor action of the memory cell such that a control voltage applied to both gate contacts is insufficient to turn off the cell.
According to an aspect of the present invention, the diffusion region is a p-type region, while the source and drain regions are n-type regions. Current flow between the source and drain regions is controlled by a control voltage applied to both gate contacts. In an unprogrammed state, current flow is enabled when the control voltage is greater than an original threshold voltage of the memory cell. During a programming operation, heat generated by the gate heating structure causes the dopant atoms in the channel to segregate towards the source and drain regions. This segregation lowers the threshold voltage of the memory cell so that current flow between the source and drain regions is enabled even when the control voltage is less than the original threshold voltage.
According to another aspect of the present invention, the diffusion region is an n-type region, and the source and drain regions are p-type regions. The polysilicon layer of the gate heating structure is doped using a p-type dopant, such as boron. Current flow between the source and drain regions is controlled by a control voltage applied to both gate contacts. In an unprogrammed state, current flow is enabled when the control voltage is less than an original threshold voltage of the memory cell. During a programming operation, heat generated by the gate heating structure induces carrier activation in the polysilicon layer, and also causes dopant atoms in the polysilicon layer to penetrate the oxide layer and lodge in the channel region of the memory cell. As a result, the threshold voltage of the memory cell is raised such that current flow between the source and drain regions is enabled even when the control voltage is greater than the original threshold voltage.
Because the memory cell of the present invention uses temperature, rather than voltage, as a programming mechanism, the present invention eliminates the prior art problems associated with high voltage generation. Also, the memory cell of the present invention does not add any complexity or cost to the IC manufacturing process. Because the heating structure is similar to a conventional polycide gate and has no floating gate, the present invention eliminates the additional process steps required by the prior art.
The present invention will be more fully understood in view of the following description and drawings.